1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device with a gate all around structure.
2. Related Art
A transistor of a simple plane type (Planer) which includes one gate electrode is generally known. In addition, there is another transistor having such a structure that a plurality of gate electrodes arranged with the transistor, which contributes to improve an electrical controllability from the gate electrodes to realize a transistor which is excellent in ON/OFF switching characteristic. The electrical controllability will be able to be enhanced by employing, for example, a gate electrode structure (Gate All Around) which encompasses an entire channel section of the transistor. JP-A-6-252403, JP-A-2003-37272 and JP-A-2003-69036 are examples of related art. Those examples disclose an example of a formation of a gate all around transistor by employing a single crystal silicon substrate (SOI (Silicon On Insulator) substrate) on an insulating film.
However, a gate all around MOSFET requires a complex manufacturing process due to a three dimensional structure of a gate electrode. Further, the silicon substrate (wafer) and the SOI substrate which are used for the gate all around MOSFET are expensive and it is difficult for those substrates to be made into a large size for the use of a display.